1. Field of the Invention
The invention relates to central processing unit (CPU) instruction decoders and more particularly to a CPU instruction decoding system which accommodates the modification of instructions by incrementation, decrementation, and by substitution of both stored and computed binary values in operand fields of an instruction during instruction execution, while providing continued CPU access to the operation code of the instruction. In addition, transfer delays caused by timing variances in transferring instructions through the decoding system to the CPU are overcome.
2. Prior Art
In CPU instruction decoding logic systems heretofore used in data processing systems, data transfer delays have been incurred which cause the CPU to enter into an idle state while awaiting a new instruction. More particularly, timing variances occur as a new CPU instruction is presented to a decoding logic system, clocked into the logic system, and supplied to the outputs of the logic system for access by the CPU.
Upon the CPU receiving an instruction from the decoding logic system, the CPU executes the operation indicated by the operation code with reference to the specified operands. Where a same operation has been performed upon plural operands, either an extended instruction set requiring a more complex decoding logic system or plural instructions have been required. Further, where continued access to a same operation code of an instruction has been required, the instruction either has been loaded repeatedly into the decoding logic system or the load input of the decoding logic system has been disabled. Either alternative substantially limits the availability of decoding logic system devices for uses other than the transfer of CPU instructions from main memory to the CPU.
In the present invention, a decoding logic system is provided which overcomes timing variances in transferring instructions to a CPU, and which is structured to accommodate continued access to the operation code of an instruction without interfering with the use of operand bits for other purposes. Further, incrementation, decrementation, and the substitution of either stored values or computed values in the operand bits of an instruction are accommodated during instruction execution.